View MP28248_7500131.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MP28248 high-efficiency, fast-transient, 3a, 4.2v-20v input synchronous step-down converter in a qfn12 (2x3mm) package MP28248 rev 1.0 www.monolithicpower.com 1 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the MP28248 is a fully-integrated, high- efficiency, synchronous, step-down, switch mode converter. it offers a very compact solution that can achieve a 3a continuous output current over a wide input supply range with excellent load and line regulation. the MP28248 operates at high efficiency over a wide output-current load range. constant-on-time control mode provides fast transient response and eases loop stabilization. full protective features include short-circuit protection, over-current protection, over-voltage protection, under-voltage protection, and thermal shutdown. the MP28248 requires a minimal number of readily-available standard external components. this device is available in a space-saving 2mmx3mm 12-pin qfn package. features ? wide 4.2v to 20v operating input range ? 3a output current ? low r ds (on) internal power mosfets ? proprietary switching-loss reduction technique ? soft startup/shutdown ? programmable switching frequency ? scp, ocp, uvp, ovp, and thermal shutdown ? output adjustable from 0.815v to 13v ? available in a qfn12 (2mmx3mm) package applications ? networking systems ? distributed power systems a ll mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps w ebsite under the products, quality a ssurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application 40 50 60 70 80 90 100 0.01 0.1 1 10 vin=12v
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 2 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number package top marking MP28248gd* qfn12 (2x3mm) acr *for tape & reel, add suffix ?z (e.g. MP28248gd?z). package reference gnd sw bst vcc en gnd sw in freq fb top view ss gnd 1 2 12 3 4 8 7 6 5 11 10 9 sw qfn12 (2x3mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 22v v sw ..................................... -0.3v to (v in + 0.3v) v bs ....................................................... v sw + 6v i vin (rms) ........................................................ 3.5a all other pins .................................. -0.3v to +6v continuous power dissipation (t a = 25c) (2) qfn12 (2x3mm)........................................ 1.8w junction temperature .............................. 150c lead temperature .................................... 260c storage temperature ............... -65c to +150c recommended operating conditions (3) supply voltage v in ........................... 4.2v to 20v output voltage v out ..................... 0.815v to 13v maximum junction temp. (t j ) ... -40c to 125c thermal resistance (4) ja jc qfn12 (2mmx3mm) ............... 70 ...... 15 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 3 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, t a = 25c, unless otherwise noted. parameters symbol condition min typ max units supply current (shutdown) i in v en = 0v 0 a supply current (quiescent) i q v en = 2v, v fb = 0.9v 440 490 a hs switch-on resistance ( 5 ) hs rds-on 120 m ? ls switch-on resistance ( 5 ) ls rds-on 50 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 1 a current limit i limit after soft-start time-out 4 5 a one-shot on-time t on r 7 = 600k ? , v out = 1.2v 480 ns r 7 = 200k ? , v out = 1.2v 160 ns r 7 = 120k ? , v out = 1.2v 100 ns minimum off time t off 125 ns fold-back off time (5) t fb -ocp il=ilim=1 fb=0.6v 5 s t fb -scp il=ilim=1 fb=0.2v 10 s ocp hold-off time (5) t oc il=ilim=1 fb=0.6v 50 s feedback voltage v fb t a =25c 807 815 823 mv feedback current i fb v fb =815mv 30 50 na en rising threshold en vth-hi 1.05 1.3 1.6 v en threshold hysteresis en vth-h y s 500 mv en input current i en v en = 2v 1.5 a v en = 0v 0 a soft-start charging current iss vss = 0v 14 a soft stop charging current iss vss=0.815v 4.5 a v in under-voltage lockout threshold rising inuv vth 3.1 v v in under-voltage lockout threshold hysteresis inuv hys 300 mv thermal shutdown t sd 150 c thermal shutdown hysteresis t sd-hys 25 c note: 5) guaranteed by design and characterization
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 4 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions qfn12 (2x3mm) pin # name description 1, 11, 12 gnd system ground. reference ground for the regulated output voltage. requires special consideration during pcb layout. 2, 10, exposed pad sw switch output. connect using wide pcb traces. 3 bst bootstrap. requires a capacitor connec ted between sw and bst pins to form a floating supply across the high-side switch driver. 4 vcc internal bias supply. decouple with a 1f ceramic capacitor as close to the pin as possible. 5 en en = 1 to enable the MP28248. for automatic start-up, connect en pin to vin with a pull-up resistor. 6 ss soft-start. connect an external ss capacitor to program the soft-start time for the switch mode regulator. when the en pin goes high, an internal curr ent source (14a) charges up the ss capacitor and the ss voltage smoothly ramps up from 0 to v fb . when the en pin goes low, an internal current source (4.5 a ) discharges the ss capacitor and the ss voltage smoothly drops. 7 fb feedback. sets the output voltage when connec ted to the tap of an external resistor divider that is connected between output and gnd. 8 freq frequency. set during ccm operation. connect a resistor r 7 to in to set the switching frequency. decouple with a 1nf capacitor. 9 in supply voltage. the MP28248 operates from a +4 .2v to +20v input rail. requires c1 to decouple the input rail. use wide pcb traces and multiple vias to make the connection.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 5 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical characteristics v in =12v, v out =1.2v, l=2 h, t a =+25c,unless otherwise noted. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 4 8 12 16 20 450 460 470 480 490 500 510 520 530 540 550 4 8 12 16 20 100 200 300 400 500 600 700 0 5 10 15 20 no load supply current vs. input voltage enable supply current vs. input voltage disable supply current vs. input voltage 4.7 4.8 4.9 5 5.1 5.2 5.3 510 15 20 i o =1.5a i o =3a i o =0a vcc vs. input voltage 5 5.04 5.08 5.12 5.16 5.2 0 0.5 1 1.5 2 2.5 3 vcc vs. io 400 410 420 430 440 450 460 470 480 4 8 12 16 20 fs vs. input voltage 0 50 100 150 200 250 300 350 400 450 500 0 0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5 4 8 12 16 20 no load bst vs. vin fs vs.output current 0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80 100 v in =4.5v v in =12v v in =20v current limit vs. temperature full load
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 6 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical characteristics (continued) v in =12v, v out =1.2v, l=2 h, t a =+25c,unless otherwise noted. 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -40 -20 0 20 40 60 80 100 5.05 5.07 5.09 5.11 5.13 5.15 -40 -20 0 20 40 60 80 100 vcc (v) 400 410 420 430 440 450 460 470 480 490 500 -40 -20 0 20 40 60 80 100 frequency(khz) 2.5 2.75 3 3.25 3.5 3.75 4 4.25 -40 -20 0 20 40 60 80 100 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -40 -20 0 20 40 60 80 100 bst voltage(v)
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 7 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted. 40 50 60 70 80 90 100 0.01 0.1 1 10 output current(a) efficiency vs. load current vo=1.2v vin=20v vin=12v vin=5v 0 200 400 600 800 1000 1200 0 0.5 1 1.5 2 2.5 3 output current(a) power loss(mw) power loss vs. load current vo=1.2v vin=20v vin=12v vin=5v 70 75 80 85 90 95 100 0.01 0.1 1 10 output current(a) vin=8v vin=20v vin=12v efficiency vs. load current 0 200 400 600 800 1000 1200 1400 1600 0 0.5 1 1.5 2 2.5 3 output current(a) power loss(mw) vin=20v vin=12v vin=8v power loss vs. load current output current(a) -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 4 8 12 16 20 input voltage(v) no load half load full load line regulation vo=1.2v 1.164 1.166 1.168 1.17 1.172 1.174 1.176 1.178 1.18 1.182 1.184 1.186 510 15 input voltage(v) output voltage(v) half load full load no load vo vs. vin vo=1.2v -1.5 -1 -0.5 0 0.5 1 1.5 0 0.5 1 1.5 2 2.5 3 vin=20v vin=12v vin=5v load regulation vo=1.2v case temperature rise vs. output current 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3 output current(a) vin=20v vin=12v vo=1.2v vo vs. io 1.16 1.165 1.17 1.175 1.18 1.185 1.19 1.195 0 0.5 1 1.5 2 2.5 3 output current(a) output voltage(v) vo=1.2v vin=20v vin=12v vin=5v
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 8 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted. shut down through vin io=3a io=0a io=3a start up through en start up through en
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 9 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 10 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. block diagram freq oc bst vcc uv detect comparator - + 5v ldo 0.4v ilim uv ov h s-fet 1meg ls-fet rsen vcc ov detect comparator + - 1.0v pwm agnd logic off timer current modulator bstreg soft start/stop loop comparator - + + xs xr hs driver q current sense amplifer sw - + ls driver gnd en in reference 0.8v start fb refresh timer ss hs ilimit comparator - + on timer over-current timer figure 1: functional block diagram
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 11 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the MP28248 is a fully-integrated, synchronous, rectified, step-down switch converter. the device uses constant-on-time (cot) control to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) turns on whenever the feedback voltage (v fb ) is lower than the reference voltage (v ref )?a low v fb indicates insufficient output voltage. the input voltage and the frequency-set resistor determine the on period as follows: ?? ?? ? 7 on in 9.3 r (k ) t40(ns) v(v) 0.4 (1) after the on period elapses, the hs-fet enters the off state. by cycling hs-fet between the on and off states, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) turns on when the hs-fet is in its off state to minimize the conduction loss. shoot-through occurs when both the hs-fet and the ls-fet are turned on at the same time, causing a dead short between input and gnd. shoot-through dramatically reduces efficiency, and the MP28248 avoids this by internally generating a dead-time (dt) between when hs- fet turns off and ls-fet turns on, and when ls-fet turns off and hs-fet turns on. heavy-load operation figure 2: heavy-load operation during heavy-load operation?when the output current is high?the MP28248 enters continuous- conduction mode (ccm) where the hs-fet and ls-fet repeat the on/off operation described for pwm operation, the inductor current never goes to zero, and the switching frequency (f sw ) is fairly constant. figure 2 shows the timing diagram during this operation. light-load operation during light-load operation?when the output current is low?the MP28248 reduces the switching frequency to maintain high efficiency, and the inductor current drops near zero. when the inductor current reaches zero, the ls-fet driver goes into tri-state (high z). the current modulator controls the ls-fet and limits the inductor current to around -1ma as shown in figure 3. hence, the output capacitors discharge slowly to gnd through ls-fet, r1, and r2. this operation greatly improv es device efficiency when the output current is low. figure 3: light-load operation light-load operation is also called skip mode because the hs-fet does not turn on as frequently as during heavy-load conditions. the frequency at which the hs-fet turns on is a function of the output current?as the output current increases, the time period that the current modulator regulates becomes shorter, and the hs-fet turns on more frequently. the switching frequency increases in turn. the output current reaches the critical level when the current modulator time is zero, and can be determined using the following equation: in out out out sw in (v -v ) v i= 2lf v ? ?? ? (2) the device reverts to pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range.
MP28248 ? 3a, 3.3v-20v input, fast transient synchronous step-down converter in 2x3mm qfn MP28248 rev. 1.0 www.monolithicpower.com 12 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. bs t n 1 lsg vc c c 3 s w l c o u t c 5 figure 4: floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection with a rising threshold of 2.2v and a hysteresis of 150mv. the bootstrap capacitor is charged from vcc through n1 (figure 4). n1 turns on when the ls- fet turns on and turns off when the ls-fet turns off. switching frequency MP28248 uses constant-on-time control because there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on-time one-shot timer through the resistor r 7 . the duty ratio is kept as v out /v in , and the switching frequency is fairly constant over the input voltage range. the switching frequency can be determined with the following equation: 6 sw 7in delay in out 10 f (khz)= 9.3 r (k ? )v(v) +t (ns) v (v)-0.4 v (v) ? ? (3) where t delay is the comparator delay, and equals approximately 40ns. MP28248 is optimized to operate at high switching frequency with high efficiency. high switching frequency makes it possible to use small-sized lc filter components to save system pcb space. jitter and fb ramp slope jitter occurs in both pwm and skip modes when the noise in the v fb ripple propagates a delay to the hs-fet driver, as shown in figure 5 and figure 6. jitter can affect system stability, with noise immunity proportional to the steepness of v fb ?s downward slope. however, v fb ripple does not directly affect noise immunity. v re f v fb hs driver v noise j itter v s l o pe1 figure 5: jitter in pwm mode v fb hs driver jitter v ref v slope2 v noise figure 6: jitter in skip mode ramp with large esr capacitor for poscap or other types of capacitors with large esr as the output capacitors, the esr ripple dominates the output ripple, and the slope on the fb is related to the esr. figure 7 shows an equivalent circuit in pwm mode with the hs- fet off and without an external ramp circuit. go to the application information section for design recommendations for large esr capacitors. figure 7: simplified circuit in pwm mode without external ramp compensation to realize a stable output without an external ramp, select an esr value using the following equation: ? ?? ? sw on esr out tt 0.7 2 r c (4) where t sw is the switching period.
MP28248 ? 3a, 3.3v-20v input, fast transient synchronous step-down converter in 2x3mm qfn MP28248 rev. 1.0 www.monolithicpower.com 13 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ramp with small esr capacitor when using ceramic output capacitors, the esr is insufficient to stabilize the system and requires external ramp compensation. the application section discusses this in further depth. . figure 8: simplified circuit in pwm mode with external ramp compensation figure 8 shows a simplified external ramp compensation circuit (r4 and c4) for pwm mode, with the hs-fet off. chose r1, r2, and c4 of the external ramp to meet the following condition: 12 9 sw 4 1 2 rr 11 <+r 2 fc5r+r ?? ? ? ?? ?? ?? (5) where: r4 c4 fb c4 iiii ??? (6) and v ramp on v fb can then be estimated as: ? ??? ?? in out 12 ramp on 44 12 9 vv r//r vt rc r//rr (7) the downward slope of the v fb ripple then follows: ? ? ?? ? out ramp slope1 off 4 4 v v v trc (8) as shown in equation 8, either reduce r4 or c4 if there is instability in pwm mode. if c4 can not be reduced further due to limitation from equation 5, then reduce r4. for stable pwm operation, design v slope1 based on equation 9. ? ? ?? sw on esr out slope1 out out sw on tt +-rc io(ma) 0.7 2 -v v + 2lc t -t (9) where i o is the load current. in skip mode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. figure 9 shows the simplified circuit of the skip mode when both the hs-fet and ls- fet are off. figure 9: simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: ?? ref slope2 12 out v v (r r //ro) c ? ? ?? (10) where r o is the equivalent load resistor. as shown in figure 6, v slope2 in skip mode is lower than that is in the pwm mode, so generally the jitter in skip mode is larger. for a system with less jitter in light-load condition, select smaller v fb resistors, though smaller resistors decrease the light-load efficiency. when using a large-esr capacitor on the output, add a 10f or smaller ceramic capacitor in parallel to minimize esl effects. soft-start/stop the MP28248 employs a soft start/stop (ss) mechanism to ensure smooth output during power up and power shut-down. when the en pin goes high, an internal current source (14 a) charges up the external ss cap. the ss cap voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage reaches v ref , it continues to ramp up while the pwm comparator only compares the v ref and the v fb . at this point, the soft start finishes and it enters into steady state operation. when the en pin goes low, an internal 4.5 a current source discharges the external ss cap voltage. once the ss voltage falls below the v ref , the pwm comparator will only compare the v fb to the ss voltage. the output voltage will decrease smoothly with the ss voltage until the voltage level zeros out at high load. the ss cap value can be determined as follows:
MP28248 ? 3a, 3.3v-20v input, fast transient synchronous step-down converter in 2x3mm qfn MP28248 rev. 1.0 www.monolithicpower.com 14 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ?? ? ? ? ? ?? ?? ? ss ss ss ref tmsi a cnf vv (11) if the output capacitors are large, avoid setting a short ss time to avoid hitting the current limit during ss. table 1 lists ss times with different external capacitor value. table 1: soft-start time vs. capacitor value t ss (ms) c ss (nf) 0.58 10 1.92 33 2.74 47 3.96 68 5.82 100 over-current protection and short-circuit protection the MP28248 has cycle-by-cycle over-current limit control that monitors the inductor current during the hs-fet on state. once the inductor current exceeds the current limit, the hs-fet turns off. at the same time, the ocp timer?set at 50s?starts. ocp will trigger if the current reaches or exceeds the current limit every cycle during those 50s, and the MP28248 enters hiccup mode to periodically restart the part. if v fb < 0.5xv ref and the current hits its limit, the MP28248 triggers the short-circuit protection (scp) immediately and the MP28248 enters hiccup mode to periodically restart the part. if v fb < 0.5xv ref and the inductor current peak value exceeds the set current limit threshold, MP28248 enters hiccup mode to periodically restart the part. this protection mode is especially useful when the output short s to ground, greatly reducing the average short-circuit current and any thermal build-up to protect the regulator. the MP28248 exits the hiccup mode once the over current condition is removed. over-voltage protection (ovp) MP28248 monitors the output voltage through the tap of a resistor divider connected to fb. when v fb exceeds 1.25xv ref , MP28248 triggers ovp. ls-fet is then left on, while the hs-fet is off. exiting ovp requires power cycling the MP28248. uvlo protection MP28248 has uvlo protection. when v in exceeds the uvlo rising threshold voltage, the chip powers up. it shuts off when v in is less than the uvlo falling threshold voltage. this is non- latch protection. thermal shutdown the junction temperature of the ic is monitored internally. if the junction temperature exceeds the threshold value (typically 150c), the converter shuts off. this is non-latch protection. there is about 25c hysteresis. once the junction temperature drops to around 125c, it initiates a soft start.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev 1.0 www.monolithicpower.com 15 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage?large esr capacitors for applications that use electrolytic or pos capacitors as output capacitors, the output voltage is set by feedback resistors r1 and r2 as shown in figure 10. figure 10: simplified circuit of pos capacitor to design the feedback circuit, first select a value for r2: a small r2 will lead to considerable quiescent current loss while a large r2 makes the fb pin noise-sensitive. for best results, choose a value between 5k ? and 50k ? for r2, and choose a comparatively larger r2 when v o is low?e.g. 1.05v?and a smaller r2 when v o is high. then determine r1 using the following equation that takes the output ripple into consideration: out out ref 12 ref 1 vvv 2 rr v ?? ? ?? (12) where out v ? is the output ripple determined by equation 21. setting the output voltage?small esr capacitors figure 11: simplified circuit with ceramic capacitor when using a low-esr ceramic capacitors on the output, add an external voltage ramp to the fb pin. as figure 11 shows, the resistive divider and the ramp voltage, v ramp , influences the output voltage. as discussed in the previous section, the v ramp can be calculated as per equation 7. select an appropriate r2: typically in the range of 5k ? to 50k ? for most applications; use a relatively large r2 when v o is low? e.g.,1.05v?and a small r2 when v o is high. determine r1 as follows: 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r (13) where v fb(avg) is the average value on the fb pin. its value in skip mode is lower than in pwm mode, meaning load regulation is strictly conditional to to the v fb(avg) . line regulation is also related to v fb(avg) . for improved load or line regulation, use a lower v ramp as per equation 9. for pwm mode, use the following equation to determine v fb(avg) : 12 fb( avg) ref ramp 12 9 r//r 1 vvv 2r//rr ?? ? ? (14) typically r9 is 0 ? , but the appropriate non-zero value, as per equation 15, improves noise immunity. select a value that is around 0.2r1//r2 to minimize its effect on v ramp . ? ?? ? 9 4sw 1 r 2c2f (15) to simplify the calculation of r1 for equation 14, add a dc-blocking capacitor, c dc , to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. approximating r1 is now much easier with c dc using equation 16 for pwm mode. ?? ? ? out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 (16) select a c dc value at least 10 the value of c4 for better dc blocking, though do not select a c dc that exceeds 0.47f to avoid long start-up times. larger c dc values improve fb noise immunity when combined with smaller r1 and r2 values to limit system start-up effects. note that even with c dc , the load and line regulation are still v ramp -related.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev. 1.0 www.monolithicpower.com 16 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. figure 12: simplified ceramic capacitor circuit with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance and should be placed as close to the v in pin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv ?? ?? (17) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 ? (18) for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as follows: out out out in sw in in in iv v v= 1- fc v v ?? ?? ?? ? ?? (19) under worst-case conditions where v in = 2v out : out in sw in i 1 v= 4f c ? ? (20) output capacitor the output capacitor maintains the dc output voltage. use ceramic or poscap capacitors for best results. the output voltage ripple can be estimated as: ?? ?? ? ? ??? out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc (21) for ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: ?? ?? ??? out out out 2 sw out in vv v(1) 8f lc v (22) the output voltage ripple caused by esr is very small and requires an external ramp to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equations 5, 8 and 9. for poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system and therefore does not need an external ramp. use a minimum esr value of around 12m ? to ensure stable converter operation. for simplification, the output ripple can be approximated as: ?? ?? ? ? out out out esr sw in vv v(1)r fl v (23) the application design must also consider the maximum output capacitor value. if the output capacitor value is too high, the output voltage can?t reach the designated value during the soft- start time, and then the device will fail to regulate. the maximum output capacitor value c o_max can be approximately by: ? ?? o_max lim_avg out ss out c(i i)t/v (24) where i lim_avg is the average start-up current during soft-start period and t ss is the soft-start time.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev. 1.0 www.monolithicpower.com 17 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. inductor the inductor supplies constant current to the output load while being driven by the switched input voltage. a larger-value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger-value inductor will have a larger physical footprint, higher series resistance, and/or lower saturation current. a good rule for determining the inductance value is to design the peak-to-peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current, and that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: out out sw l in vv l= (1- ) f iv ? ? (25) where i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, where the peak inductor current can be calculated by: ?? ?? ? out out lp out sw in vv ii (1 ) 2f l v (26) design example some design examples with typical outputs are provided in the following tables: table 2: 1.2v v out (l = 2 h) v in v out (v) r7 r4 c4 r1 r2 f sw (v) ( ? ) ( ? ) (f) ( ? ) ( ? ) (hz) 12 1.2 301k 806k 220p 17.4k 40.2k 440k table 3: 1.8v v out (l = 2 h) v in v out (v) r7 r4 c4 r1 r2 f sw (v) ( ? ) ( ? ) (f) ( ? ) ( ? ) (hz) 12 1.8 402k 649k 220p 30k 24.3k 500k table 4: 2.5v v out (l = 2 h) v in v out (v) r7 r4 c4 r1 r2 f sw (v) ( ? ) ( ? ) (f) ( ? ) ( ? ) (hz) 12 2.5 499k 499k 330p 21.5k 10k 544k table 5: 3.3v v out (l = 4.7 h) v in v out (v) r7 r4 c4 r1 r2 f sw (v) ( ? ) ( ? ) (f) ( ? ) ( ? )(hz) 12 3.3 680k 806k 330p 31.6k 10k 520k table 6: 5v v out (l = 8 h) v in v out (v) r7 r4 c4 r1 r2 f sw (v) ( ? ) ( ? ) (f) ( ? ) ( ? ) (hz) 12 5 1m 1.2m 220p 53.6k 10k 544k the detailed application schematic is shown in figure 13. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board data sheets. typical application schematic en vin 25v c1a c5 301k r7 806k r4 sw 220pf c4 1210 c2b ns c2d ns j1 ss 1.2v@3a gnd vcc gnd ns r8 ns d1 c3 40.2k r2 1210 0603 c2a c2c 7443552200 499k r5 1nf c7 0 r3 0 r9 17.4k r1 vout l1 MP28248 ss 6 vcc 4 gnd 11 gnd 12 freq 8 en 5 in 9 sw 2 gnd 1 fb 7 bst 3 sw 10 u1 33nf c6 vout 4.2v-20v figure 13: detailed application schematic
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) MP28248 rev. 1.0 www.monolithicpower.com 18 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1) the high current paths (gnd, in, and sw) should be placed very close to the device with short, wide, and direct traces. 2) put the input capacitors as close to the in and gnd pins as possible. 3) put the decoupling capacitor as close to the v cc and gnd pins as possible. 4) keep the switching node sw short and away from the feedback network. the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 5) keep the bst voltage path (bst, r3, c3, and sw) as short as possible. 6) use a four-layer board to achieve better thermal performance.
MP28248 ? 3a, 4.2v-20v input, fast-transient sy nchronous step-down converter in qfn12 (2x3mm) notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP28248 rev 1.0 www.monolithicpower.com 19 1/5/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn12 (2x3mm) side view top view bottom view 1.90 2.10 2.90 3.10 0.00 0.05 pin 1 id marking recommended land pattern note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference drawing is jedec mo-220 5) drawing is not to scale. pin 1 id index area 1 11 7 5 0.45 0.55 0.50 bsc 0.20 0.30 0.35 0.45 0.80 1.00 0.20 ref 6 12 0.35 0.45 0.60 0.50 0.25 1.90 0.70 0.00 1.10 0.35 0.45 0.40 0.35 0.45 0.00 1.30 0.20 0.20 0.30 1.45 0.90 0.25 1.80 0.70 0.25 0.60

▲Up To Search▲

Price & Availability of MP28248

	To Download MP28248 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .